The present invention relates to a semiconductor device in which a plurality of semiconductor chips are mounted onto one package using a relay wiring substrate (interposer), and a manufacturing method thereof.
FIG. 2 is a configuration diagram of a conventional semiconductor device described in a patent document 1 (Japanese Unexamined Patent Publication No. 2003-78104).
The semiconductor device includes lower-stage semiconductor chips or elements 101 and 102 face-down mounted in such a manner that their circuit surfaces face a multilayer circuit substrate 200, and an upper-stage semiconductor chip or element 103 mounted astride the two semiconductor elements 101 and 102. The semiconductor element 103 is face-down mounted in such a manner that its circuit surface faces the semiconductor elements 101 and 102.
The semiconductor element 101 is electrically connected to primary pads 211 of the multilayer circuit substrate 200 by gold bumps 121 formed on their corresponding pads 111. An adhesive or bonding resin 401 is interposed between the semiconductor element 101 and the multilayer circuit substrate 200. Incidentally, the semiconductor element 102 is also connected to the multilayer circuit substrate 200 in a manner similar to the semiconductor element 101.
On the other hand, each of pads 113 formed on the circuit surface of the semiconductor element 103 is electrically connected to a primary pad 213 formed on the surface of the multilayer circuit substrate 200 via a tape wiring 301 and a bonding wire 302. The tape wiring 301 and each of the semiconductor elements 101 and 102 are electrically connected by an insulating layer 402.
The respective primary pads 211 and 213 of the multilayer circuit substrate 200 are respectively connected to secondary pads 241 and 243 provided on the back surface of the multilayer circuit substrate 200 via through holes. External terminals 261 and 263 are provided on the secondary pads 241 and 243 respectively.
The semiconductor element mounting face side of the multilayer circuit substrate 200 is sealed with a resin 408. A metal heat radiating plate 410 is mounted on the back surface of the semiconductor element 103 through a thermal conducive adhesive or bonding material 409 interposed therebetween.
According to such a layered semiconductor device, it can efficiently diffuse heat generated at the semiconductor element 103 large in heating value through the heat radiating plate 410 and is suitable even for heat radiation into chassis or casing or the like.
Although, however, the heat generated at the semiconductor element 103 can be radiated through the heat radiating plate 410 provided on the back surface of the semiconductor element 103 in the semiconductor device, the heat generated at the inner semiconductor elements 101 and 102 cannot be radiated. Therefore, there is a fear that a radiating effect is not sufficient as the case may be, and the inner semiconductor elements 101 and 102 are subjected to high temperatures, thereby causing a malfunction.